The present invention relates to an electrostatic discharge (ESD) protection device, and more particularly, to an ESD structure with high ESD robustness in high-voltage CMOS process.
In CMOS integrated circuits (IC) technology, damage due to ESD events is a critical issue. Advanced technologies such as thin gate oxidation, short channel length, shallow junction, salicidation, etc., result in ICs having lower ESD endurance. According to the current industrial standard, the input and output pins of IC products must sustain the ESD stress of over 2000 V in human-body-model (HBM) and over 200 V in machine-model (MM) ESD stresses. Therefore, the ESD protection circuit must be disposed around the input and output (I/O) pads of an IC to provide ESD stress protection.
Increasing numbers of automotive and consumer products such as print head drivers, are used in high voltage areas. The typical layout and cross-section views with ESD protection device utilized in high voltage is shown in FIGS. 1a and 1b. The N type heavily doped source region 11 and the gate terminal 13 of the NMOS 1 are coupled to a ground (GND) and a n-well 14 is formed below the N type heavily doped drain region 12 to serve as a buffer layer. When an ESD event occurs, high current flows through the parasitic lateral BJT of the NMOS 1 to the ground protecting internal circuit. Most of the ESD current however flows through a corner of the N type heavily doped drain region 12 due to the tip discharge theorem. Thus most of the current accumulates at the corner and the interface at the corner of the N type heavily doped drain region 12 generally breaks down, resulting in a non-uniform current flow problem.
In U.S. Pat. No. 6,258,672; Shih, et al. describes another ESD protection device, in which the gate electrode has a variable width and thus the channel region has a variable length. The previously described problem, however still exists.